NXP Semiconductors /MIMXRT1064 /CAN1 /CTRL1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PROPSEG 0 (LOM_0)LOM 0 (LBUF_0)LBUF 0 (TSYN_0)TSYN 0 (BOFFREC_0)BOFFREC 0 (SMP_0)SMP 0 (RWRNMSK_0)RWRNMSK 0 (TWRNMSK_0)TWRNMSK 0 (LPB_0)LPB 0 (ERRMSK_0)ERRMSK 0 (BOFFMSK_0)BOFFMSK 0PSEG20PSEG10RJW0PRESDIV

BOFFMSK=BOFFMSK_0, LBUF=LBUF_0, ERRMSK=ERRMSK_0, BOFFREC=BOFFREC_0, SMP=SMP_0, LPB=LPB_0, TSYN=TSYN_0, LOM=LOM_0, TWRNMSK=TWRNMSK_0, RWRNMSK=RWRNMSK_0

Description

Control 1 Register

Fields

PROPSEG

This 3-bit field defines the length of the Propagation Segment in the bit time

LOM

This bit configures FLEXCAN to operate in Listen Only Mode

0 (LOM_0): Listen Only Mode is deactivated

1 (LOM_1): FLEXCAN module operates in Listen Only Mode

LBUF

This bit defines the ordering mechanism for Message Buffer transmission

0 (LBUF_0): Buffer with highest priority is transmitted first

1 (LBUF_1): Lowest number buffer is transmitted first

TSYN

This bit enables a mechanism that resets the free-running timer each time a message is received in Message Buffer 0

0 (TSYN_0): Timer Sync feature disabled

1 (TSYN_1): Timer Sync feature enabled

BOFFREC

This bit defines how FLEXCAN recovers from Bus Off state

0 (BOFFREC_0): Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B

1 (BOFFREC_1): Automatic recovering from Bus Off state disabled

SMP

This bit defines the sampling mode of CAN bits at the FLEXCAN_RX

0 (SMP_0): Just one sample is used to determine the bit value

1 (SMP_1): Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used

RWRNMSK

This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register

0 (RWRNMSK_0): Rx Warning Interrupt disabled

1 (RWRNMSK_1): Rx Warning Interrupt enabled

TWRNMSK

This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register

0 (TWRNMSK_0): Tx Warning Interrupt disabled

1 (TWRNMSK_1): Tx Warning Interrupt enabled

LPB

This bit configures FlexCAN to operate in Loop-Back Mode

0 (LPB_0): Loop Back disabled

1 (LPB_1): Loop Back enabled

ERRMSK

This bit provides a mask for the Error Interrupt.

0 (ERRMSK_0): Error interrupt disabled

1 (ERRMSK_1): Error interrupt enabled

BOFFMSK

This bit provides a mask for the Bus Off Interrupt.

0 (BOFFMSK_0): Bus Off interrupt disabled

1 (BOFFMSK_1): Bus Off interrupt enabled

PSEG2

This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time

PSEG1

This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time

RJW

This 2-bit field defines the maximum number of time quanta One time quantum is equal to the Sclock period

PRESDIV

This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency

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